1. Field of the Invention
The invention relates to an insulating gate type semiconductor device, and a method of fabricating the same, and more particularly to an insulating gate type semiconductor device such as vertical MOSFET as a power supplier and MOSFET modulating electrical conductivity, and a method of fabricating the same.
2. Description of the Related Art
FIG. 1 illustrates vertical MOSFET having a source region formed in a self-align fashion without carrying out photolithography steps.
The illustrated MOSFET includes a semiconductor region 1 including an N.sup.+ type semiconductor substrate 2, and an epitaxial layer 3 formed at a surface of the N.sup.+ type semiconductor substrate 2. The epitaxial layer 3 includes a P-type base region 4 formed at a surface of the epitaxial layer 3 in a selected region, an N.sup.+ source region 5 formed at a surface of the base region 4 in a selected region, and an N.sup.- drain region 6 constituted of the epitaxial layer 3 as it is except the base region 4 and the source region 5. The epitaxial layer 3 is formed with a recess 7 passing throughout the source region 5 and reaching an intermediate depth of the base region 4.
A gate oxide film 8 is formed on the epitaxial layer 3 so that it covers the drain region 6, the base region 4, and a part of the source region 5 therewith, and a gate electrode 9 composed of polysilicon is formed on the gate oxide film 8.
An interlayer insulating film 10 covers the gate electrode 9 and a part of the source region 5 therewith. A source electrode 11 covers the interlayer insulating film 10, and a part of the source region 5 around the recess 7, and fills the recess 7 therewith. A drain electrode 12 is formed at a lower surface of the semiconductor substrate 2.
Japanese Unexamined Patent Publication No. 4-314365 has suggested a method of fabricating MOSFET illustrated in FIG. 1. Hereinbelow is explained the method.
First, a semiconductor region 1 including an N.sup.+ type semiconductor substrate 2, and an epitaxial layer 3 formed on the semiconductor substrate 2 and lightly doped with N-type impurities is thermally oxidized at a surface thereof to thereby form a gate oxide film 8 at a surface of the semiconductor region 1.
Then, a polysilicon film is formed on the gate oxide film 8, and a photoresist film pattern is formed on the polysilicon film. Thereafter, both the gate oxide film 8 and the polysilicon film are etched with the photoresist film pattern being used as a mask, to thereby form a window through which the epitaxial layer 3 is exposed. Then, boron (B) and arsenic (As) are successively ion-implanted into the epitaxial layer 3 through the window, followed by thermal diffusion, to thereby form a base region 4 and a source region 5 in the epitaxial layer 3.
Then, an interlayer insulating film 10 is deposited all over the product. After forming a photoresist film pattern on the interlayer insulating film 10, the interlayer insulating film 10 is etched with the photoresist film pattern being used as a mask, to thereby form a contact hole. Then, the epitaxial layer 3 is etched again with the photoresist film pattern being used as a mask again, to thereby form a recess 7 throughout the source region 5.
After over-etching the interlayer insulating film 10, the photoresist film pattern is removed. At this stage, an inner surface of the recess 7 and a part of the source region 5 are exposed. Then, metal is deposited over the product, and unnecessary portions of the metal are etched for removal. Thus, the source electrode 11 is completed. Then, metal is evaporated onto a lower surface of the semiconductor substrate 2 to thereby form a drain electrode 12.
Though FIG. 1 illustrates MOSFET constituted of a single cell, MOSFET is actually constituted of a plurality of cells. A gate polysilicon wiring layer is formed on the epitaxial layer 3 with a field oxide layer sandwiched therebetween concurrently with the gate electrode 9. After forming an interlayer insulating film on the polysilicon wiring layer, a gate metal wiring layer is also formed on the interlayer insulating film concurrently with the source electrode 11 so that the gate metal wiring layer makes electrical contact with the gate polysilicon wiring layer. The gate electrodes 9 of the cells are electrically in connection with gate pads through the gate polysilicon wiring layer and the gate metal wiring layer.
The above-mentioned method has a problem as follows.
In the above-mentioned method, when a contact between the gate polysilicon wiring layer and the gate metal wiring layer is made concurrently with a contact between the source and base regions 4, 5 and the source electrode 11, the latter contact being made by etching the interlayer insulating film 10 with a photoresist film pattern being used as a mask, to thereby form a contact hole therethrough, etching the epitaxial layer 3 with the photoresist film pattern being used again as a mask, to thereby form the recess 7, and over-etching the interlayer insulating film 10, there may be formed a recess passing through the gate polysilicon wiring layer in dependence on a thickness of the gate polysilicon wiring layer. As a result, while the interlayer insulating film 10 is being etched, the field oxide film is also over-etched through the recess passing through the gate polysilicon wiring layer, and further side-etched below the gate polysilicon layer, which causes the field oxide layer to have a reduced thickness, and also causes less reliability. In the worst case, the gate metal wiring layer may be short-circuited with the semiconductor region 1.